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10511 sy/82609 sy im no.1514-1/20 LE24CBK22 overview the dual port eeprom series consists of two independent banks, and each bank can be controlled separately using dedicated control pins. the two banks can each be controlled separately, but share the internal power supply system. in addition, this product uses a 2-wire se rial interface, and is the optimal device for realizing substantial reductions in system cost and mounting area, as well as low power consumption. the dual port eeprom series also has a combined mode that allows the two-bank configuration (2k bits + 2k bits) to be used as a pseudo one-bank configuration (4k bits) by setting the cobm pin low. together with the 16-byte page write function, this enables a reduction in the number of factory write processes. this product incorporates sanyo's high performance cmos eeprom technology and realizes high-speed operation and high-level reliability. the interface of this product is compatible with the i 2 c bus protocol, making it ideal as a nonvolatile memory for small-scale parameter storage. in addition, this product also supports ddc2 tm , so it can also be used as an edid data storage memory for display equipment. functions ? capacity : 2k bits (256 8 bits) + 2k bits (256 8 bits), 4k bits in total ? bank structure : 2 banks (2k bits + 2k bits) ? single supply voltage : 2.5v to 5.5v ? interface : two wire serial interface (i 2 c bus * ), vesa ddc2 tm compliant ** ? operating clock frequency : 400khz (max) ? low power consumption : standby: 5 a (max) : active (read): 0.5ma (max) continued on next page. ordering number : en*a1514a cmos ic two wire serial interface eeprom (2k+2k eeprom) * : i 2 c bus is a trademark of philips corporation. ** : ddc and edid are trademarks of video electronics standard association (vesa). * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LE24CBK22 no.1514-2/20 continued from preceding page. ? automatic page write mode: 16 bytes ? read mode : sequential read and random read ? erase/write cycles : 10 6 cycles ? data retention : 20 years ? high reliability : adopts sanyo?s proprietary sy mmetric memory array configuration (usp6947325) noise filters connected to scl1, sda2, scl2 and sda2 pins incorporates a feature to prohibit write operations under low voltage conditions. ? package : LE24CBK22m mfp8 (225mil) : LE24CBK22tt msop8 (150mil) package dimensions package dimensions unit:mm (typ) unit:mm (typ) 3032e [LE24CBK22m] 3245b [LE24CBK22tt] pin assignment pin descriptions pin.1 scl2 serial clock input pin.2 sda2 serial data input/output (for bank2) pin.3 cobm bank/combine mode switching pin.4 gnd ground pin.5 sda1 serial data input/output pin.6 scl1 serial clock input (for bank1) pin.7 wp write protect pin.8 v dd power supply gnd 1 2 3 4 8 7 6 5 scl2 sda2 cobm v dd wp scl1 sda1 sanyo : msop8(150mil) 3.0 1.1max 3.0 0.5 4.9 12 8 0.25 0.65 (0.53) (0.85) 0.125 0.08 sanyo : mfp8(225mil) 12 8 5.0 0.63 6.4 0.15 0.35 1.27 (0.6) 4.4 (1.5) 1.7 max 0.1
LE24CBK22 no.1514-3/20 block diagram description of operation the bank1 control signals are scl1 and sda1, and the bank 2 control signals are scl2 an d sda2. the control signals for each bank can be controlled separately, regardless of the ot her bank's status. this enables behavior like two separate eeprom mounted in a single package, enabling the bank1 and bank2 sides to be used simultaneously for two independent systems. bank mode (2k bits + 2k bits) and combined mode (internally treated as 4k bits) can be switched using the cobm pin. in combined mode, the bank1 control signals (scl1, sda1 ) are used, and both bank1 and bank2 are accessed. this enables the two-bank configuration (2k bits + 2k bits) to be used as a pseudo one-bank configuration (4k bits), which allows access to both the bank1 and bank2 areas using a si ngle system of control signals (scl1, sda1). data correlation is guaranteed between combined mode and bank mode, enabling operation while switching the mode, such as performing write in combined mode and read in bank mode. i/o buffer sda1 eeprom array (2k-bit) x decoder high voltage generator serial-parallel converter address generator y decoder & sense amp condition detector serial controller write controller input buffer scl1 eeprom array (2k-bit) x decoder high voltage generator serial-parallel converter address generator y decoder & sense amp condition detector serial controller write controller bank controller & mode decoder i/o buffer sda2 bank1 bank2 wp input buffer cobm scl2 input buffer
LE24CBK22 no.1514-4/20 specifications absolute maximum ratings parameter symbol conditions ratings unit supply voltage -0.5 to +6.5 v dc input voltage -0.5 to +5.5 v over-shoot voltage below 20ns -1.0 to +6.5 v storage temperature tstg -65 to +150 c note: if an electrical stress exceeding the maximu m rating is applied, the device may be damaged. operating conditions parameter symbol conditions ratings unit operating supply voltage 2.5 to 5.5 v operating temperature -40 to +85 c dc electrical characteristics v dd =2.5v to 5.5v parameter symbol conditions min typ max unit supply current at reading (when either bank1 or bank2 is read) i cc 11 f=400khz 0.5 ma supply current at reading (when both bank1 and bank2 are read simultaneously) i cc 12 f=400khz 0.8 ma supply current at writing (when either bank1 or bank2 is written) i cc 21 f=400khz, t wc =5ms 5 ma supply current at writing (when both bank1 and bank2 are written simultaneously) i cc 22 f=400khz, t wc =5ms 8 ma standby current i sb v in =v dd or gnd 0.7 5 a input leakage current i li v in =gnd to v dd -2.0 +2.0 a output leakage current (sda) i lo v out =gnd to v dd -2.0 +2.0 a input low voltage v il v dd *0.3 v input high voltage v ih v dd *0.7 v i ol =0.7ma, v dd =2.5v 0.2 v i ol =3.0ma, v dd =2.5v 0.4 v i ol =3.0ma, v dd =5.5v 0.4 v output low voltage v ol i ol =6.0ma, v dd =4.5v 0.6 v capacitance /ta=25 c, f=100khz parameter symbol conditions min typ max unit in/output capacitance c i/o v i/o =0v (sda) 2 5 pf input capacitance c i v in =0v (other than sda) 2 5 pf note: this parameter is sampled and not 100% tested.
LE24CBK22 no.1514-5/20 ac electric characteristics fast mode v dd =2.5v to 5.5v parameter symbol min typ max unit slave mode scl clock frequency f scls 0 400 khz scl clock low time t low 1200 ns scl clock high time t high 600 ns sda output delay time t aa 100 900 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 600 ns start condition hold time t hd.sta 600 ns data in setup time t su.dat 100 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 600 ns scl, sda rise time t r 300 ns scl, sda fall time t f 300 ns bus release time t buf 1200 ns noise suppression time t sp 100 ns write cycle time t wc 5 ms standard mode v dd =2.5v to 5.5v parameter symbol min typ max unit slave mode scl clock frequency f scls 0 100 khz scl clock low time t low 4700 ns scl clock high time t high 4000 ns sda output delay time t aa 100 3500 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 4700 ns start condition hold time t hd.sta 4000 ns data in setup time t su.dat 250 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 4000 ns scl, sda rise time t r 1000 ns scl, sda fall time t f 300 ns bus release time t buf 4700 ns noise suppression time t sp 100 ns write cycle time t wc 5 ms bus timing t buf t su.sto t r scl sda/in sda/out t su.sta t hd.dat t high t low t su.dat t dh t aa t f t hd.sta t sp t sp
LE24CBK22 no.1514-6/20 write timing pin functions (for bank1) scl1 (serial clock input) pin the scl1 pin is the serial clock input pin used to access the bank1 area, and pro cesses signals at th e rising and falling edges of the scl1 clock signal. this pin must be pulled up by a resistor to the v dd level, and wired-ored with another open drain (or open collector) output device for use. in combined mode, the scl1 pin is serial clock input pin controlled both bank1 and bank2. sda1 (serial data input/output) pin the sda1 pin is used to transfer serial data to the input/output of the bank1 side area and it consists of a signal input pin and n-channel transistor open drain output pin. like the scl1 line, the sda1 line must be pulled up by a resistor to the v dd level and wired-ored with another open drain (or open collector) output device for use. in combined mode, the sda1 pin is serial data input/output pin controlled both bank1 and bank2. (for bank2) scl2 (serial clock input) pin the scl2 pin is the serial clock input pin used to access the bank2 area, and pro cesses signals at th e rising and falling edges of the scl2 clock signal. this pin must be pulled up by a resistor to the v dd level, and wired-ored with another open drain (or open collector) output device for use. in combined mode, the scl2 pin is invalid. sda2 (serial data input/output) pin the sda2 pin is used to transfer serial data to the input/output of the bank2 side area and it consists of a signal input pin and n-channel transistor open drain output pin. like the scl2 line, the sda2 line must be pulled up by a resistor to the v dd level and wired-ored with another open drain (or open collector) output device for use. in combined mode, the sda2 pin is invalid. (shared pins) wp (write protect) pin when the wp pin is high, write protect is enabled, and wr ite is prohibited to all memory areas within both bank1 and bank2. read operation can access all memory areas regardless of the wp pin status. cobm (combined mode) pin the cobm pin is used to switch the eeprom internal operation between bank mode and combined mode. the eeprom operates in bank mode when the cobm pin is high, and in combined mode when low. note that in combined mode, the scl2 an d sda2 pins are treated as don?t care. t wc scl sda d0 write data acknowledge stop condition start condition
LE24CBK22 no.1514-7/20 functional description 1. start condition when the scl line is at the high level, the start condition is established by changing the sda line from high to low. the operation of the eeprom as a slave starts in the start condition. 2. stop condition when the scl line is at the high level, the stop condition is established by changing the sda line from low to high. when the device is set up for the read sequence, the read operation is suspended when th e stop condition is received, and the device is set to standby mode. when it is set up for the write sequence, the capture of the write data is ended when the stop condition is received, and the eeprom internal write operation is started. 3. data transfer data is transferred by changing the sd a line while the scl line is low. when the sda line is changed while the scl line is high, the resulting condition will be recognized as the start or stop condition. stop condition start condition scl sda t su.sta t hd.sta t su.sto scl sda t su.dat t hd.dat
LE24CBK22 no.1514-8/20 4. acknowledge during data transfer, 8 bits are transf erred in succession, and then in the nint h clock cycle period the device on the system bus receiving the data sets the sda line to low, and sends the acknowledge signal indicating that the data has been received. the ackn owledge signal is not sent during an eeprom internal write operation. 5. device addressing for the purposes of communication, the master device in the system generates the start condition for the slave device. communication with a particular slave device is enabled by sending along the sda bus the device address, which is 7 bits long, and the read/write command code, which is 1 bit long, immediately following the start condition. the upper four bits of the device address are called the device code which, for this product, is fixed as ?1010.? this device has the upper 3-bit of the slave device address as the slave address (bank1: sa2, sa1, sa0 and bank2: sb2, sb1, sb0), which fixed internally. the value of slave address are sa2=0, sa1=0, sa0=0 and sb2=0, sb1=0, b0=0 when the device code input from sda and the slave addresse s are compared with the pro duct?s device code and slave addresses that were set at the mounti ng stage and found to match, the product sends the acknowledge signal during the ninth clock cycle period, and initiates the read or write operation in accordance with the read or write command code. if they do not match, the eeprom returns to standby mode. when a read operation is performed immediately after the slave device has been switched, the random read command must be used. * the default internal slave address is set to sa2 = 0, sa1 = 0, sa0 = 0. * in bank mode (2k bits), the valid address is a7 to a0, and the valid slave address is sa2, sa1 and sa0. * in combined mode (4k bits), the valid address is a8 to a0, and the slave address sa2 and sa1 is don?t care. a8 = 0: selects the bank1 area, a8 = 1: selects the bank2 area. valid address slave address bank mode ( cobm =?h?) a7-a0 sa2, sa1, sa0 combine mode ( cobm =?l?) a8-a0 a8=0: selects the bank1 area a8=1: selects the bank2 area sa2, sa1 but sa2 and sa1 are don?t care. 1 0 1 0 sa2 sa1 sa0 or a8 r/w acknowledge bit output start condition scl (eeprom input) sda (master output) sda (eeprom output) 1 8 9 t aa t dh bank1 device code slave address msb lsb device address word
LE24CBK22 no.1514-9/20 * the default internal slave address is set to sb2 = 0, sb1 = 0, sb0 = 0. * in combine mode (4k bits), communication in bank2 side is invalid. valid address slave address bank mode ( cobm =?h?) a7-a0 sb2, sb1, sb0 combine mode ( cobm =?l?) - - 6. internal mode the eeprom functions in bank mode when the cobm pin is high, or in combined mode when the cobm pin is low. 6-1. bank mode the eeprom functions in bank mode when the cobm pin is high. in bank mode, each bank (bank1, bank2) is controlled separately using dedicated control signals. the two banks are independent, and can be controlled separately regardless of the other bank's status. this enables treatment like two separate eeprom mounted in a single package, which means that the bank 1 and bank2 sides can be connected to the mcu of separate systems. 1 0 1 0 sb2 sb1 sb0 r/w bank2 slave address device code msb lsb device address word scl1 sda1 scl2 sda2 LE24CBK22 00h ffh bank1 (2k-bit ) 00 h ffh bank2 (2k-bit ) wp
LE24CBK22 no.1514-10/20 6-2. combine mode the eeprom functions in combined mode when the cobm pin is low. in combined mode, the bank1 control signals scl1 and sda1 are used to control both bank1 and bank2. combined mode uses the two-bank configuration (2k bits + 2k bits) as a pseudo one-bank configuration (4k bits). in combined mode, the bank2 control signals scl2 and sda2 are treated as don?t care. in combined mode, the memory area is processed as a 4k-bit single bank, so the msb address changes from a7 to a8, and a8 becomes a valid address. set a8 = 0 to control the bank1 area, or a8 = 1 to control the bank2 area. data correlation is guaranteed between combined mode an d bank mode, enabling operation while switching the mode, such as performing write in combined mode and read in bank mode. 7 eeprom write operation 7-1. byte writing when the eeprom receives the 7-bit device address an d write command code ?0? after the start condition, it generates an acknowledge signal. after this, if it receives the 8-bit word addr ess, generates an acknowledge signal, receives the 8-bit write data, generates an acknowledge signal and then receives the stop condition, the internal write operation of the eeprom in the designated memory ad dress will start. rewriting is completed in the t wc period after the stop condition. during an eeprom internal write oper ation, no input is accepted and no acknowledge signals are generated. in bank mode: s2, s1, and s0 are valid. in combined mode: a8 is valid. s2 and s1 are don?t care. 1 0 1 0 x x a8 r/w device code slave address msb lsb device address word bank1 x: don?t care scl1 sda1 wp scl2 sda2 LE24CBK22 000h 0 ffh bank1 (2k-bit) 100h 1ffh bank2 (2k-bit) access from master word address 0 1 0 s1 1 w start ack ack ack sto p sda a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 data r/w s2 s0/ a8
LE24CBK22 no.1514-11/20 7-2. page writing this product enables pages with up to 16 bytes to be written. the basic data transfer procedure is the same as for byte writing: following the start condition, the 7-bit device addr ess and write command code ?0,? word address (n), and data (n) are input in this order while confirming acknowledge ?0? every 9 bits. the page write mode is established if, after data (n) is input, the write data (n+1) is input w ithout inputting the stop condition. after this, the write data equivalent to the largest page size can be received by a continuous process of repeatin g the receiving of the 8-bit write data and generating the acknowledge signals. at the point when the write data (n+1) has been input, the lower 4 bits (a0-a3) of the word addresses are automatically incremented to form the (n +1) address. in this way, the write data can be successively input, and the word address on the page is incremente d each time the write data is input. if th e write data exceeds 16 bytes or the last address of the page is exceeded, the word address on the page is rolled over. write data will be input into the same address two or more times, but in such cases the write data that was input last will take effect. finally, the eeprom internal write operation corresp onding to the page size for which the wr ite data is received starts from the designated memory address when the stop condition is received. in bank mode: s2, s1, and s0 are valid. in combined mode: a8 is valid. s2 and s1 are don?t care. 7-3. acknowledge polling acknowledge polling is used to find out when the eeprom internal write operation is completed. when the stop condition is received and the eeprom starts rewriting, all opera tions are prohibited, and no response can be given to the signals sent by the master device. therefore, in orde r to find out when the eeprom internal write operation is completed, the start condition, device address and write command code are sent from the master device to the eeprom (slave device), and the respon se of the slave device is detected. in other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been completed. sda memory address(n) ack sto p d7 d6 - d1 d0 d7 d6 - d1 d0 d7 d6 - d1 d0 d7 d6 - d1 d0 ack ack ? ? data ( n+x ) 0 1 0 1 w start ack ack a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 data ( n ) ack d7 d6 - d1 d0 ack ? ? ? ?
LE24CBK22 no.1514-12/20 8 eeprom read operations 8-1. current address reading the address equivalent to the memory address accessed last +1 is held as the internal address of the eeprom for both write* and read operations. theref ore, provided that the master device has recognized the position of the eeprom address pointer, data can be read from the memory address with the current address pointer without specifying the word address. as with writing, current address read ing involves receiving the 7-bit device address and read command code ?1? following the start condition, at which time the eeprom gene rates an acknowledge signal. after this, the 8-bit data of the (n+1) address is output serially starting with the highest bits. after the 8 bits have been output, by not sending an acknowledge signal and inputting the stop condition, the eeprom completes the read operation and is set to standby mode. if the previous read address is the last address, the address for the current address reading is rolled over to become address 0. *: if the last address (a3-a0=1111b) on the page has been designated at the write operation as the word address, the first address (a3-a0=0000b) on the page se rves as the internal address after writing. 8-2. random read random read is a mode in which any memory address is sp ecified and its data read. the address is specified by a dummy write input. first, when the eeprom receives the 7-bit device address and write command code ?0? following the start condition, it generates an acknowledge signal. it then receives the 8-bit word address, and generates an acknowledge signal. through these operations, the word address is load ed into the address count er inside the eeprom. next, the start condition is input again and the current read is initiated. this causes the data of the word address that was input using the dummy write input to be output. if, after the data is output, an acknowledge signal is not sent and the stop condition is input, reading is completed, and the eeprom returns to standby mode. device address 0 1 0 1 r start ack no ack sto p sda d7d6d5d4d3d2d1d0 data(n+1) r/w s1 s2 s0/ a8 in bank mode: s2, s1, and s0 are valid. in combined mode: a8 is valid. s2 and s1 are don?t care. access from master d7 - d0 data ( n ) word address ( n ) 0 1 0 1 w start ack ack sda a7 a6 a5 a4 a3 a2 a1 a0 device address 0 10 1 r start ack no ack sto p dummy write device address current read r/w r/w s1 s2 s0/ a8 s1 s2 s0/ a8 in bank mode: s2, s1, and s0 are valid. in combined mode: a8 is valid. s2 and s1 are don?t care. access from maste
LE24CBK22 no.1514-13/20 8-3. sequential read in this mode, the data is read continuously, and sequential read operations can be performed with both current address read and random read. if, after the 8-bit data has been output, acknowledge ?0? is input and reading is continued without issuing the stop condition, the address is increm ented, and the data of the next address is output. if acknowledge ?0? continues to be input after the data has been output in this way, the data is successively output while the address is incremented. when the last address is reached, it is roll ed over to address 0, and the data continues to be read. as with current address read and random read, the operation is completed by inputting the stop condition without sending an acknowledge signal. d7 d6 - d1 d0 data (n) sda device address 0 1 0 1 r start ack no ack sto p d7 d6 - d1 d0 data (n+1) ack ack d7 d6 - d1 d0 data (n+x) r/w s1 s2 access from maste in bank mode: s2, s1, and s0 are valid. in combined mode: a8 is valid. s2 and s1 are don?t care. s0/ a8
LE24CBK22 no.1514-14/20 application notes 1) software reset function software reset (start condition + 9 dummy clock cycles + st art condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. during the dummy clock input period, the sda bus must be opened (set to high by a pull-up resistor). since it is possible for the ack output and read data to be output from the eeprom during the dummy clock period, forcibly entering h will result in an overcurrent flow. note that this software reset function does not work during the internal write cycle. 2) pull-up resistor of sda pin due to the demands of the i 2 c bus protocol function, the sda pin must be connected to a pull-up resistor (with a resistance from several k to several tens of k ) without fail. the appropriate value must be selected for this resistance (r pu ) on the basis of the v il and i il of the microcontroller and other devices controlling this product as well as the v ol ?i ol characteristics of the product. generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. r pu maximum resistance the maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (i l ) of the input leaks of the devices connected to the sda bus and by r pu , can completely satisfy the input high level (v ih min) of the microcontroller and eeprom. however, a resistance value that satisfies sda rise time t r and fall time t f must be set. r pu maximum value = (v dd - v ih )/i l example: when v dd =3.0v and i l = 2 a r pu maximum value = (3.0v ? 3.0v 0.8)/2 a = 300k r pu minimum value a resistance corresponding to the low-level output voltage (v ol max) of sanyo?s eeprom must be set. r pu minimum value = (v dd ? v ol )/i ol example: when v dd =3.0v, v ol = 0.4v and i ol = 1ma r pu minimum value = (3.0v ? 0.4)/1ma = 2.6k recommended r pu setting r pu is set to strike a good balance between the operating frequency requirements and power consumption. if it is assumed that the sda load capacitance is 50pf and the sda output data strobe time is 500ns, r pu will be about r pu = 500ns/50pf = 10k . start condition scl sda 1 2 8 9 dummy clock cycle
LE24CBK22 no.1514-15/20 3) precautions when turning on the power this product contains a power-on reset circuit for prev enting the inadvertent writing of data when the power is turned on. the following conditions must be met in order to ensure stable operation of this circuit. no data guarantees are given in the event of an instantaneous power failure during the internal write operation. v dd =2.5 to 5.5v item symbol min typ max unit power rise time t rise 100 ms power off time t off 10 ms power bottom voltage v bot 0.2 v notes: 1) the sda pin must be set to high and the scl pin to low or high. 2) steps must be taken to ensure that the sda and scl pins are not placed in a high-impedance state. a. if it is not possible to satisfy the instruction 1 in note above, and sda is set to low during power rise after the power has stabilized, the scl and sda pins must be controlled as shown below, with both pins set to high. b. if it is not possible to satisfy the instruction 2 in note above after the power has stabilized, soft ware reset must be executed. c. if it is not possible to satisfy the instructions both 1 and 2 in note above after the power has stabilized, the steps in a must be executed, then software reset must be executed. 4) noise filter for the scl and sda pins this product contains a filter circuit for eliminating noise at the scl and sda pins. pulses of 100ns or less are not recognized because of this function. 5) function to inhibit writing when supply voltage is low this product contains a supply voltage monitoring circu it that inhibits inadvertent writing below the guaranteed operating supply voltage range. the data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3v and below. 6) slave address settings this product does not come with any slave address pins, but the information of the bank1: sa2, sa1, sa0 and bank2: sb2, sb1, sb0 slave addresses is held internally. sa2=0, sa1=0, sa0=0 and sb2=0, sb1=0, sb0=0 were set for the slave addresses before ship ment. during device addressing, these slave address codes must be executed following the device code. v dd 0v t off t rise vbot v dd scl sda t low t dh t su.dat v dd scl sda t su.dat
LE24CBK22 no.1514-16/20 7) note on write protect operation this product prohibits writing to all memory areas when the wp pin is high. to ensure full write protection, the wp pin is set high for all periods from the start condition to the stop condition, and the condition below must be satisfied. v dd =2.5 to 5.5v item symbol min typ max unit wp setup time t su.wp 600 ns wp hold time t hd.wp 600 ns 8) notes on mode switching this product selects bank mode operation or combined mode operation according to the cobm pin status. changing the cobm pin status while this product is active (during acce ss to bank1 or bank2, in cluding during the write period) is prohibited. the following conditions must be observed to ensure reliabl e access functions in each mode. v dd =2.5 to 5.5v item symbol min typ max unit cobm setup time t su .cobm 10 s cobm hold time (write cycle time) t hd .cobm 5 ms stop condition start condition scl sda t su.wp t hd.wp wp stop condition start condition scl t su.cobm t hd.cobm cobm sda
LE24CBK22 no.1514-17/20 9) write using a rom writer in combined mode this product enters combined mode by setting the cobm pin (pin 3) low, which allows the two-bank configuration (2k bits + 2k bits) to be used as a pseudo one-bank conf iguration (4k bits). this en ables write using a rom writer in the manner of a typical 4k-bit eeprom. pin 3 of standard 4k-bit eeprom products is assigned a slave pin (s2), but pin 3 of the LE24CBK22 is assigned the cobm pin. combined mode is entered by setting the cobm pin low. in combined mode, the state of the scl2 pin and sda2 pin is "don't care" (may be either high, low, or open). rom writer connection example in combined mode, the slave addres s (sa2, sa1) is don't care, and any combination can be entered (sa2 = 1, sa1 = 1 or sa2 = 1, sa1 = 0 or sa2 = 0, sa1 = 1 or sa2 = 0, sa1 = 0). 1 0 1 0 sa2 sa1 a8 r/w gnd scl2 sda2 cobm 1 2 3 4 8 7 6 5 v dd wp scl1 sda1 LE24CBK22 1 2 3 4 8 7 6 5 gnd v dd wp scl sda s0 s1 s2 le24c04x (standard 4k-bit eeprom) 1 2 3 4 8 7 6 5 scl2 sda2 LE24CBK22 (don?t care) gnd v dd wp scl1 sda1 cobm connect to gnd level device code slave address msb lsb device address word in combined mode: (from scl1/sda1)
LE24CBK22 no.1514-18/20 memory area (4k-bit) the msb address in combined mode is a8. a8 is used to select the bank1 or bank2 area. set a8 = 0 to control the bank1 area, or a8 = 1 to control the bank2 area. 10) system configuration image (hdmi system) this product can support two hdmi ports simultaneously. each port can be accessed (read operation, write operation) constantly, regardless of the other port?s status. 000h bank1 (2k-bit) 0ffh 100h bank2 (2k-bit) 1ffh a8=0 a8=1 lcd-tv LE24CBK22 level shifter level shifter hdmi connector hdmi connector tmds tmds ddc ddc i 2 c i 2 c bank1 bank2 hdmi receiver image processor
LE24CBK22 no.1514-19/20 11) peripheral circuit diagram example of connection with hdmi receiver *1: system power supply (3v) for hdmi receiver, etc. *2: reverse-current preventing diode this device can be operated by supplying power from any of the connected hdmi connectors (ddc + 5v) or the system power supply (3v). however, the supply voltage must be set so that the voltage stepped-down by the reverse-current preventing diode is within the gu aranteed operation voltage range of this device. *3: level shifter when connecting the 5v hdmi connector side with a 3v syst em, level shifters must generally be inserted. however, this is not necessary when the hdmi receiver supports 5v input signals. *4: write protect in general after implementation, use with hdmi applications presumes that this device performs read-only operation. the write protect function is enabled to prevent write due to mi staken access, by setting th e wp pin to the same level as the power supply (8: v dd ) for this device. note that the wp pin is connected to the power supply via a resistor, and that when re-settings, etc., is necessary, write operation is enabled by connecting the wp pin to gnd level using jumpers, etc. *5: pull-up resistors for the i 2 c and ddc interfaces. see item 2) in the application notes for the resistance value settings. hdmi connector ddc+5v ddc_clk ddc_dat gnd hdmi connector ddc+5v ddc_clk ddc_dat gnd LE24CBK22 8:v dd 6:scl1 5:sda1 1:scl2 2:sda2 7:wp level shifter level shifter 3: cobm v dd (3v) *1 hdmi receiver v dd (3v) 4:gnd scl1(3v) sda1(3v) scl2(3v) sda2(3v) *2 *2 *2 *3 *3 *4 *5 rpu *5 rpu
LE24CBK22 no.1514-20/20 ps this catalog provides information as of january, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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